The present invention relates to a control apparatus for an external memory and an information processing system, and more in particular to a control apparatus (abbreviated as "DKC") carrying a cache memory for an external memory like a disk unit (abbreviated as "DKU").
In recently-developed computer systems, a memory in the central processing unit (CPU) such as a cache memory has an access time as high in speed as several nanoseconds (ns) to several tens of nanoseconds, and a main storage (MS) in the CPU several tens of ns to one hundred and several tens of ns. Further, the processing speed of the central processing unit is in the order of picoseconds (ps) in terms of the gate delay time of a large-scale logic integrated circuit constituting the central processing unit.
In a magnetic disk unit or the like which is a kind of DASD (Direct Access Storage Device) connected to a high-speed central processing unit and playing an important role especially as an external memory for storing a large amount of data, on the other hand, the access time is approximately several tens of ms (milliseconds) at most in view of the mechanical operations such as head seeking and the rotational delay (time) of the magnetic disk providing a storage. The data transfer speed of this device, which is several hundred ns per byte, is also low as compared with that of the central processing unit, so that the amount of data exchangeable per unit time is limited. This limitation in data throughput makes up a great bottleneck for improving the processing capacity of the computer system as a whole.
Generally, a great amount of data stored in an external memory has a comparatively narrow range accessible from the central processing unit within a predetermined time. In other words, it has a local reference characteristic.
In view of this, the prior art as disclosed in JP-A-59-100964 is well known, in which a cache memory is provided on an external memory control unit arranged on the central processing unit side between a plurality of channels and an external memory such as a magnetic disk unit for controlling inputs to and outputs from external units in place of the central processing unit. This cache memory includes a semiconductor memory or the like accessible at a speed higher than the magnetic disk unit. Among the data stored in the magnetic disk unit, those ones expected to have a high probability of access are copied in the cache memory from time to time, and a request for access to the data in the magnetic disk unit from a channel is met with high speed by using the data copied in the cache memory as far as possible (at about 70% to 80% in cache hit rate). The chances of direct access to the external memory having a large access time from a channel are thus reduced, thereby improving the processing capacity, that is, throughput of the whole system.
In the aforementioned prior art system, the external memory control unit is provided with a function of performing data exchange in parallel fashion both between a plurality of channels and a cache memory and between a cache memory and an external memory. The control function of the external memory control unit permits data exchange between the channels and the external memory in the case where the data exchange between the channels and the cache memory competes with that between the cache memory and the external memory.
The above-mentioned prior art system fails to take into consideration the number of data transfer routes between the channels and the cache memory and between the cache memory and the external memory, both of which have the same number of routes. If the data required for access in each of data transfer routes or passages between the channels and the cache memory happens to be lacking in the cache memory by what is called a "cache miss" and the need arises for direct access to the external memory, therefore, all the data transfer routes on the channel side come to be connected to the data transfer routes on the external memory side, and are thus entirely occupied in what is called the busy state between DKC and DKU. Under this condition, even if a request arises from another channel for access to the data in the cache memory, the external memory is incapable of receiving the request, thus posing the problem of the cache memory being not utilized effectively.
This means that a central processing unit is required to wait before a request for access to the data in the external memory is met, with the result that the data throughput between the channels and the external memory is reduced, thereby contributing to a reduced performance of the computer system as a whole.